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CIF Peripheral Model - SimpleTimer
82 CoMET Version 5.9 – Tutorial
Registers
The SimpleTimer requires registers to enable and configure the timer, as well as provide a
mechanism for the embedded target software to communicate with the device. The timer has
the following registers:
General Timer Register (GTR)
The General Timer (GT) is the reference timer used by the Match Timers. It consists of a 32-
bit counter register called the General Timer Register (GTR). The CPU can directly read or
write the GTR, but only as an entire word (4-byte value).
Register is readable and writeable
Value after reset = 0x00000000;
Address offset: 0x00;
Match Timer Registers (MTR1 and MTR2)
Each Match Timer Register is a 32-bit compare timer, which generates an interrupt when the
Match Timer Register value is equal to the General Timer Register value, if the
corresponding Timer Enable Register (TER) and Timer Interrupt Enable Register (TIER) bit
is set. The Match time is equal to the MTR value multiplied by the timer clock period.
The CPU can directly read and write MTR1 and MTR2, but only as entire words (4-byte
values).
Registers are readable and writeable
Value after reset = 0x00000000;
Address offset: MTR1: 0x28, MTR2: 0x30;
Bit
31
Bit
30
Bit
29
Bit
28
Bit
27
Bit
26
Bit
25
Bit
24
Bit
23
Bit
22
Bit
21
Bit
20
Bit
19
Bit
18
Bit
17
Bit
16
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
MSB
LSB
Upper 16 bits of the free running counter value
Lower 16 bits of the free running counter value
- Version 5.9 3
- Contents 5
- Contents 7
- Introduction 11
- Standalone C - Hello World 13
- Creating a Source File 17
- Adding a Build Configuration 20
- Key Points 23
- CIF Module - SimpleVSP 25
- Constructing a VSP in CoMET 26
- The SimpleVSP Example 26
- CIF Module - SimpleVSP 27
- Prerequisites 28
- Viewing the .fmx File as XML 37
- Viewing the Fmx Report 46
- Adding a Net, XML Tree View 47
- Adding Ports 56
- Checking Connections 60
- Building the VirtualPlatform 61
- Building a Project 62
- Adding a Target Image 73
- Simulating SimpleVSP1 74
- Unconnected Ports 75
- Debugging a Simulation 76
- Enabling Bus Monitoring 78
- Analyzing the VCD 80
- Obtaining a Metrix Trace 81
- Overview 83
- Specification 85
- Registers 86
- Timer Enable Register (TER) 87
- Parameters 89
- Adding Tasks 95
- Name Type 96
- MatchInterrupt1 Master 96
- MatchInterrupt2 Master 96
- TimerClock Slave 96
- Adding Behavioral Code 97
- Defining Macros 102
- Building the Project 105
- Modify Reset function 112
- CODE ENDS 115
- Creating the IrqNet 121
- Creating Target Code 124
- Adding the Target Image 129
- Metrix Output 132
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